Irvine, CA · Available 2026
ML SYSTEMS · COMPILERS · ACCELERATORS
I build the path from tensor expressions to efficient hardware execution—compiler passes, optimized kernels, and edge inference systems.
Proof, not promises.
High-level tensor expressions lowered into generated, layout-aware C++ loop kernels.
tensor shapes validated
against NumPy + PyTorch
Implemented matmul, transpose, reductions, softmax, LayerNorm, ReLU, and INT8 quantize/dequantize. Added shape tracking and fusion for add-ReLU and matmul-bias patterns.
Naive, reordered, and tiled kernels evaluated under a simulated 64 KB SRAM budget.
THROUGHPUT
IMPROVEMENT
Swept 8×8 through 64×64 tile sizes. HLS loop pipelining and array partitioning reduced estimated latency by 2.7×.
A hardware/software inference stack spanning programmable logic and PYNQ host control.
OVER ARM CPU
BASELINE
Offloaded convolution and fully connected layers while maintaining model accuracy within 1% of the software baseline.
CURRENT / CORSA LAB · UC IRVINE
Researching partial symbolic distillation and high-level synthesis for compact, hardware-aware edge inference.
The work replaces selected DNN layers with analytic expressions produced through symbolic regression, then evaluates the resulting hybrid models across accuracy, latency, and hardware resource use.
Associate Engineer — Machine Learning
inference latency improvement through batched prediction, result caching, and optimized output schemas.
Built and deployed a production recommendation engine with 90% active-catalog coverage across international e-commerce markets.
Validated ranking quality and data consistency across 28 countries.
LANGUAGESC · C++ · Python · Verilog · SystemVerilog
ML / IRPyTorch · ONNX · TorchScript · TVM · NumPy
HARDWAREVitis HLS · Vivado · PYNQ · Kria KR260
SYSTEMSLinux · Git · Bash · Docker · Kubernetes