A mini tensor compiler that lowers high-level tensor expressions into generated, layout-aware C++ loop kernels—validating outputs against PyTorch.
Implemented matmul, transpose, reductions, softmax, LayerNorm, ReLU, and INT8 quantize/dequantize with fusion support for add-ReLU patterns.
Swept 8×8 through 64×64 tile sizes. HLS loop pipelining and array partitioning reduced estimated latency by 2.7×.
Partial symbolic distillation replaces selected DNN layers with analytic expressions, evaluated across accuracy, latency, and hardware resources.
Swarnalata Panigrahy researches and builds systems at the intersection of machine learning and hardware.
Graduate researcher at CORSA Lab, UC Irvine, working on NeuSym-HLS—partial symbolic distillation for compact edge inference.
Inference runtimes, compiler lowering, performance-critical kernels, and hardware-aware acceleration.