SWARNALATA(1) ML SYSTEMS SWARNALATA(1)
NAME
swarnalata — engineer focused on inference runtimes, compiler lowering, performance-critical kernels, and accelerator-aware systems.
SYNOPSIS
inference · CUDA/Triton · C++ · compiler IR · profiling · accelerator systems
SELECTED WORK
| Name | Description | Evidence |
|---|---|---|
| tensor-compiler | Tensor expressions lowered into generated C++ loops | source / report |
| tiled-matmul | Tiling and reuse under a 64 KB SRAM budget | 4.1× |
| kr260-dnn | FPGA offload with PYNQ host control | 3.2× |
| inference-serving | Production recommendation engine with batch optimization | 31% |
RESEARCH
NeuSym-HLS
- Objective
- Partial symbolic distillation for compact edge inference models
- Method
- Replace selected DNN layers with analytic expressions via symbolic regression, then evaluate through HLS synthesis
- Evaluation axes
- Model accuracy, inference latency, hardware resource utilization (LUT, DSP, BRAM)
- Status
- Active research at CORSA Lab, UC Irvine
NOTES
BENCHMARKS
| Operator | Shape | Dtype | Hardware | Baseline | Candidate | Latency (μs) | Speedup |
|---|---|---|---|---|---|---|---|
| matmul | 512×512 | FP32 | Vivado HLS | Naive | Tiled 64×64 | 4.1× | |
| conv2d | 224×224×3 | INT8 | Kria KR260 | CPU | PL Offload | 3.2× |
python benchmarks/run.py --operator rmsnorm --dtype fp16 --shape 4096
SEE ALSO